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PRO-LINX TM GS7025
Serial Digital Receiver
PRELIMINARY DATA SHEET FEATURES * SMPTE 259M-C compliant (270Mb/s) * automatic cable equalization (typically greater than 350m of high quality cable) * serial data outputs muted and serial clock remains active when input data is lost * operation independent of SAV/EAV sync signals * signal strength indicator output * carrier detect with programmable threshold level * power savings mode (output serial clock disable) * large IJT, typically 0.56UI beyond loop bandwidth * robust lock detect APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M-C. DESCRIPTION The GS7025 provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 35dB of gain at 135MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. The GS7025 requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS7025 has dedicated pins to indicate signal strength, carrier detect, and LOCK. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS7025 provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also be disabled to reduce power. The GS7025 operates from a single +5 or -5 volt supply. ORDERING INFORMATION
PART NUMBER GS7025-CQM GS7025-CTM PACKAGE 44 pin MQFP Tray 44 pin MQFP Tape TEMPERATURE 0C to 70C 0C to 70C
GS7025
A/D DDI DDI ANALOG DIGITAL MUX CARRIER DETECT PHASELOCK HARMONIC COSC LOCK LOGIC MUTE SDO SDI SDI +
-
VARIABLE GAIN EQ STAGE
FREQUENCY ACQUISITION PHASE DETECTOR
SDO CLK_EN SCO SCO
OEM_TEST
EYE MONITOR AUTO EQ CONTROL CHARGE PUMP LF+ LFS LF-
+ AGC CAP CD_ADJ SSI/CD
VCO
CBG RVCO
BLOCK DIAGRAM
Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com
Document No. 522 - 80 - 00
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VCC + 0.5 to VEE - 0.5V 0C TA 70C
GS7025
-65C TS 150C 260C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Supply Voltage Supply Current
CONDITION
MIN 4.75
TYPICAL 5 115 125 2.5
1
MAX 5.25
UNITS V mA
NOTES
TEST LEVEL 1 1
CLK_EN = 0 CLK_EN = 1
VEE+(VDIFF/2) 200
SDI Common Mode Voltage DDI Common Mode Input Voltage Range DDI Differential Input Drive SSI/CD Output Current Source, CLMAX = 50pF, RL = open cct. Source, CLMAX = 50pF, RL=5K Sink AGC Common Mode Voltage OEM_TEST Bias Potential A/D High Low 270, CLK_EN, IN _ENABLE Input Voltage CLK_EN Input Voltage High Low High Low
VCC-(VDIFF/2) 2000 18
V V 2
1 1
0.4 to 4.6
800 -
mV A
1 3
-
-
-
110
A
3
2.0 2.0 2.5 -
1.0 2.7 4.5 -
1.5 0.8 0.8 0.8
mA V V V 5
3 1 1 1
V
1
V
1
2
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DC ELECTRICAL CHARACTERISTICS (continued)
VCC = 5.0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER LOCK Output Sink Current CLK_EN Source Current
CONDITION
MIN 500
TYPICAL 26
1
MAX 55
UNITS A A
NOTES 3
TEST LEVEL 1 1
Low
-
NOTES 1. TYPICAL - measured on characterization board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pullup resistor. 4. If OEM_TEST is permanently enabled, operating temperature range is limited from 0C to 60C inclusive. TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
GS7025
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Serial Data Rate Maximum Equalizer Gain (see Figure 3) Additive Jitter [Pseudorandom (2 Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter [Pathological (SDI checkfield)] Input Jitter Tolerance Lock Time Synchronous Switch
23 23
CONDITIONS SDI @ 135MHz
MIN -
TYPICAL
1
MAX -
UNITS Mb/s dB
NOTES
TEST LEVEL 1 7
270 (only) 35
-1)]
270Mb/s, 300m (Belden 8281) 270Mb/s
-
300
-
ps p-p
2, 7
3
-
185
-
ps p-p
2, 6
4
-1)] 270Mb/s 462 ps p-p 2, 6 1
270Mb/s tswitch < 0.5s, 270Mb/s 0.5s< tswitch <10ms tswitch > 10 ms
0.40 0.5 -200
0.56 1 1 4 1 0 800 300 10 1.0 20
2 200 1000 400 -
UI p-p s ms ms s ps mV p-p ps k pF dB
3, 6 4
1 7
Carrier Loss Time SDO to SCO Synchronization SDO, SCO Output Signal Swing SDO, SCO Rise & Fall times SDI/SDI Input Resistance SDI/SDI Input Capacitance SDI/SDI Input Return Loss at 270MHz 75 DC load 20%-80%
5
7 7 1 7
600 200 15
7 7 7
6 6 6
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AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 25C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF
PARAMETER Carrier Detect Response Time
CONDITIONS Carrier Applied, CL<50pF, RL=open cct.
MIN -
TYPICAL 3
1
MAX -
UNITS s
NOTES 7
TEST LEVEL 6
GS7025
Carrier Removed, CL<50pF, RL=open cct.
-
30
-
NOTES 1. TYPICAL - measured on characterization board. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). 5. Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed.
6. Using the DDI input, A/D=0. 7. Using the SDI input, A/D=1.
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product.
DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER
BELDEN 8281 CABLE CHARACTERIZATION BOARD TEKTRONIX GigaBERT 1400 ANALYZER TRIGGER
CLOCK
Fig. 1 Test Setup for Figures 5 and 6
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PIN CONNECTIONS
OEM_TEST
CLK_EN
SSI/CD
VCC_75
LOCK
COSC
MOD
44 DDI DDI VCC_75 VCC VEE SDI SDI VCC VEE CD_ADJ AGC1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
38 37
36
35 34
VCC
A/D
VEE
VEE
GS7025
33 32 31 30
VEE SDO SDO VEE SCO SCO VEE nc nc 270 nc
GS7025
TOP VIEW
29 28 27 26 25 24 23
13
14
15
16
17
18 19
20
21 22
AGC+
RVCO
CBG
PIN DESCRIPTIONS
NUMBER 1, 2 3, 44 4, 8, 13, 22, 35 5, 9, 14, 18, 27, 30, 33, 34, 37 6, 7 10 11, 12 15, 16, 17 19 20 21 23, 25, 26 24 28, 29 SYMBOL DDI/DDI VCC_75 VCC VEE SDI/SDI CD_ADJ AGC-, AGC+ LF+, LFS, LFRVCO_RTN RVCO CBG nc 270 SCO/SCO TYPE I I I I DESCRIPTION Digital data inputs (Differential ECL/PECL). Power supply connection for internal 75 pullup resistors connected to DDI/DDI. Most positive power supply connection. Most negative power supply connection.
I I I I I I I I O
Differential analog data inputs. Carrier detect threshold adjust. External AGC capacitor. Loop filter component connection. RVCO Return. Frequency setting resistor. Internal bandgap voltage filter capacitor. No connect - Do not connect to power or ground. Leave floating. 270Mb/s Data Rate Select - Always set high. Serial clock output. SCO/SCO are differential current mode outputs and require external 75 pullup resistors. Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75 pullup resistors.
31, 32
SDO/SDO
O
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RVCO_RTN
VCC
VCC
VEE
LF+
LFS
LF-
VEE
PIN DESCRIPTIONS (continued)
NUMBER 36 38 39 SYMBOL CLK_EN TYPE I I O DESCRIPTION Clock enable. When HIGH, the serial clock outputs are enabled. Timing control capacitor for internal system clock. Lock indication. When HIGH, the GS7025 is locked. LOCK is an open collector output and requires an external 10k pullup resistor. Signal strength indicator/Carrier detect. Analog/Digital select. 270 Mb/s modulus select - Always set high. Output `Eye' monitor test. Single-ended current mode output that requires an external 50 pullup resistor. This feature is recommended for debugging purposes only. If enabled during normal operation, the maximum operating temperature is rated to 60C.
COSC
LOCK
GS7025
40 41 42 43
SSI/CD A/D MOD OEM_TEST
O I I O
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TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25C unless otherwise shown)
5.00 450 400 4.50 350
SSI/CD OUTPUT VOLTAGE (V)
(Characterized)
4.00
JITTER (ps p-p)
300 250
GS7025
3.50
200 150 100 50
270Mb/s
3.00
2.50 0 50 100 150 200 250 300 350 400 450 500
0 0 50 100 150 200 250 300 350 400
CABLE LENGTH (m)
CABLE LENGTH (m)
Fig. 2 SSI/CD Voltage vs. Cable Length (Belden 8281) (CD_ADJ = 0V)
Fig. 5 Typical Additive Jitter vs. Input Cable Length (Belden 8281) Pseudorandom (2 -1)
23
50 45 40 35
GAIN (dB)
30 25 20 15 10 5 0 1 10 100 1000
FREQUENCY (MHz)
Fig. 3 Equalizer Gain vs. Frequency
Fig. 6 Intrinsic Jitter (2
23
- 1 Pattern) 270Mb/s
5.0
0.600 0.550
4.5
CD_ADJ VOLTAGE (V)
0.500 4.0 0.450
270Mb/s
IJT (UI)
250 300 350 400
3.5
0.400 0.350 0.300
3.0
2.5 0.250 2.0 200 0.200
0
10
20
30
40
50
60
70
CABLE LENGTH (m)
TEMPERATURE (C)
Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics
Fig. 7 Typical IJT vs. Temperature (VCC = 5.0V) (Characterized)
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DETAILED DESCRIPTION The GS7025 Serial Digital Receiver is a bipolar integrated circuit containing a built-in cable equalizer and reclocker. Serial digital signals are applied to either the analog SDI/SDI or digital DDI/DDI inputs. Signals applied to the SDI/SDI inputs are equalized and then passed to a multiplexer. Signals applied to the DDI/DDI inputs bypass the equalizer and go directly to the multiplexer. The analog/digital select pin (A/D) determines which signal is then passed to the reclocker. Packaged in a 44 pin MQFP, the receiver operates from a single 5V supply at a data rate of 270Mb/s.
1. CABLE EQUALIZER
SSI/CD OUTPUT VOLTAGE (V)
5
4
3 CD_ADJ CONTROL RANGE 2
GS7025
1
0
0
50
100
150
200
250
300
350
400
450
500
CABLE LENGTH (m)
The automatic cable equalizer is designed to equalize a serial digital data rate of 270Mb/s. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single-endedly. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 35dB of gain at 135MHz which typically results in equalization of greater than 350m of Belden 8281 cable at 270Mb/s. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its corrective level irrespective of shifts due to AC coupling.
1-1. Signal Strength Indication/Carrier Detect
Fig. 8 SSI/CD Voltage vs. Cable Length
When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8 V) and can be used to drive other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected, the SDO/SDO outputs are muted (set to a known static state).
1-2. Carrier Detect Threshold Adjust
This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. To alleviate this problem, the GS7025 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings have also been provided to give the user total flexibility. The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin (see Figure 4). The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit (see Typical Application Circuit). The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. In noisy environments, it is not recommended to leave this pin floating. Connecting this pin to VEE disables the SDO/SDO muting function and allows for maximum possible cable length equalization.
1-3. Output Eye Monitor Test
The GS7025 incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure 2 and Figure 8. With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. 8
GENNUM CORPORATION
The GS7025 also provides an 'Output Eye Monitor Test' (OEM_TEST) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM_TEST pin is an open collector current output that requires an external 50 pullup resistor. When the pullup resistor is not used, the OEM_TEST block is disabled and the internal OEM_TEST circuit is powered down. The OEM_TEST
522 - 80 - 00
provides a 100mVp-p signal when driving a 50 oscilloscope input. Due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation.
2. RECLOCKER
2-2. VCO
The reclocker receives a differential serial data stream from the internal multiplexer. It locks an internal clock to the incoming data. It outputs the differential PECL retimed data signal on SDO/SDO. It outputs the recovered clock on SCO/ SCO. The timing between the output and clock signals is shown in Figure 9.
The VCO is a differential low phase noise, factory trimmed oscillator that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO has a pull range of 15% about the centre frequency. A single low impedance external resistor, RVCO, sets the VCO centre frequency. The low impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. The recommended RVCO value applications is 365. for SMPTE 259M-C
GS7025
SDO
When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the 270Mb/s centre frequency to the limits shown in Table1.
TABLE 1: Frequency Drift Range FREQUENCY MIN (%) -13 MAX(%) 28
SCO
50%
270Mb/s lock
2-3. Phase Detector Fig. 9 Output and Clock Signal Timing
The reclocker contains three main functional blocks: the Phase Locked Loop, Frequency Acquisition, and Logic Circuit.
2-1. Phase Locked Loop (PLL)
The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the PLL.
2-4. Charge Pump
The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown below. The main components are the VCO, the phase detector, the charge pump, and the loop filter.
2
DDI/DDI
PHASE DETECTOR INTERNAL PLL CLOCK
The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. This makes the GS7025 ideal for SMPTE 259M-C applications where pathological signals have data transition densities of 0.05.
2-5. Loop Filter
CHARGE PUMP LF+ LFS LF-
VCO
The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS7025 increased immunity to PCB board noise. The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Choosing these component values is discussed in detail in the PLL DESIGN GUIDELINES section. Recommended values for SMPTE 259M-C applications are shown in the Typical Application Circuit. No further changes from the recommended GS7025 loop filter components are necessary.
RVCO LOOP FILTER
RLF CLF1 CLF2
Fig. 10 Simplified Block Diagram of the PLL
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3. FREQUENCY ACQUISITION
4. LOCKING
The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock, the GS7025 uses a frequency acquisition circuit. The frequency acquisition circuit sweeps the VCO control voltage so that the VCO frequency changes from -10% to +10% of the centre frequency. Figure 11 shows a typical sweep waveform.
tswp tsys
The GS7025 indicates valid lock when the following three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked.
GS7025
3. The system is not locked to an integer-multiple harmonic of a 270Mb/s SMPTE 259M-C signal. The GS7025 defines the presence of input data when at least one data transition occurs every 1s. The GS7025 assumes that it is NOT locked to a harmonic if the pattern `101' or `010' (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150s. In a harmonically locked system, all bit cells are double clocked and the above patterns become `110011' and `001100', respectively.
4-1. Lock Time
VLF
A Tcycle Tcycle = tswp + tsys
Fig. 11 Typical Sweep Waveform
The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The system is designed such that the probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. The average sweep time, tswp, is determined by the loop filter component, CLF1, and the charge pump current, CP: 4C LF1 t SWP = ---------------3I CP The nominal sweep time is approximately 121s when CLF1 = 15nF and CP = 165A (RVCO = 365). An internal system clock determines tsys (see section 3-1, Logic Circuit).
3-1. Logic Circuit
Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). When input data to the GS7025 is removed, the GS7025 latches the current state. Therefore, when data is reapplied, the GS7025 begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS7025 locks very quickly. The nominal lock time depends on the switching time and is summarized in the Table 3.
TABLE 3. SWITCHING TIME <0.5s 0.5s - 10ms >10ms LOCK TIME 10s 2tsys 2Tcycle + 2tsys
The GS7025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: t sys = 9.6 x 10 x C OSC [ sec onds ] The recommended value for tsys is 450s (COSC = 4.7nF)
4
To acquire lock, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys. The nominal value of Tcycle for the GS7025 operating in a typical SMPTE 259M-C application is approximately 1.3ms. The GS7025 has a dedicated LOCK output (pin 39) indicating when the device is locked. It should be noted that in synchronous switching applications where the switching time is less than 0.5s, the LOCK output will NOT be de-asserted and the data outputs will NOT be muted.
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5. OUTPUT DATA MUTING
1. Input signal amplitudes are between 200 and 2000mV. 2. The common mode input voltage range is as specified in the DC Characteristics table. Commonly used interface examples are shown in Figures 14 to 16. Figure 14 illustrates the simplest interface to the GS7025 digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry.
The GS7025 internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 12.
DDI NO DATA TRANSITIONS
GS7025
LOCK
SDO
VALID DATA
OUTPUTS MUTED
VALID DATA
DDI GS7025 DDI
Fig. 12 Output Data Muting Timing 6. CLOCK ENABLE
When CLK_EN is high, the GS7025 SCO/SCO outputs are enabled. When CLK_EN is low, the SCO/SCO outputs are placed in a high Z state and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC.
7. STRESSFULL DATA PATTERNS
Fig. 14
All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). The GS7025 is designed to operate with low data transition densities such as the SMPTE 259M-C pathological signal (data transition density = 0.05).
8. I/O DESCRIPTION 8-1. High Speed Analog Inputs (SDI/SDI)
When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 15. In this case, a parallel resistor (RLOAD) is placed near the GS7025 inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. In addition, place series resistors (RSOURCE) near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100, RSOURCE = 50 and ZO = 50.
RSOURCE RSOURCE ZO ZO DDI RLOAD DDI GS7025
Fig. 15
SDI/SDI are high impedance inputs differential or single-ended input drive.
which
accept
Figure 13 shows the recommended interface when a singleended serial digital signal is used.
75 75 113 10nF SDI 10nF GS7025 SDI
Figure 16 shows the recommended interface when the GS7025 digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used.
DDI ZO DDI GS7025
Fig. 16 Fig. 13 8-2. High Speed Digital Inputs (DDI/DDI)
DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs:
When the DDI and the DDI inputs are not used, saturate one input of the differential amplifier for improved noise immunity. To saturate, connect either pins 44 and 1 or pins 2 and 3 to VCC. Leave the other pair floating.
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8-3. High Speed Outputs (SDO/SDO and SCO/SCO)
SDO/SDO and SCO/SCO are current mode outputs that require external pullups (see Figure 17). The output signal swings are 800mV when 75 resistors are used. To shift the signal levels down by approximately 0.7 volts, place a diode between VCC and the pullups. When the output traces are longer than 1in, use controlled impedance traces. Place the pullup resistors at the end of the output traces as they terminate the trace in its characteristic impedance (75).
VCC
75 SDO SDO GS7025 SCO SCO 75 VCC
75
GS7025
75
Fig. 17
TYPICAL APPLICATION CIRCUIT
VCC VCC 10k VCC VCC 4n7
44 43 42 41 40 39 38 37 36 35 34
VCC VCC VCC VCC
SSI/CD
A/D
OEM_TEST
LOCK
MOD
CLK_EN
COSC
VCC
VEE
VCC_75
VEE
1
DDI DDI
VEE
33
4 x 75 see Note 2
from GS9024
see Note 1 2 3 4 5 6
SDO 32 SDO 31 VEE 30 To GS9020
VCC VCC 75
15nH
VCC_75 VCC VEE SDI SDI VCC VEE RVCO_RTN CD_ADJ AGC+ AGC-
GS7025 TOP VIEW
SCO 29 SCO 28 VEE 27 nc 26 nc 25
270 24
RVCO
75 37.5 VCC
10n
7
75 10n VCC
8 9 10 11
100k Pot (Optional) 0.1
VCC
nc 23
CBG
21
VCC
VEE
LF+
LFS
12 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. Power supply decoupling capacitors are not shown.
13
14
15
16
17
18
VEE
LF-
19
20
22
VCC
0.1
VCC
1.8k 15n 3.3p
365 (1%)
VCC 0.1 0.1
NOTES 1. It is recommended that the DDI/DDI inpute are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used.
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PACKAGE DIMENSIONS
13.20 0.25 10.00 0.10
GS7025
13.20 0.25 10.00 0.10
PIN 1
0.80 BSC
0.45 MAX 0.30 MIN
5 to 16
0.20 MIN 0 MIN 0.3 MAX. RADIUS 7 MAX 0 MIN
2.20 MAX 1.85 MIN 0.23 MAX. All dimensions in millimetres
2.55 MAX 5 to 16 0.13 MIN. RADIUS 1.60 REF 0.88 NOM.
0.35 MAX 0.15 MIN
44 pin MQFP
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change.
REVISION NOTES: New document.
For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright November 2000 Gennum Corporation. All rights reserved. Printed in Canada.
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